SerDes Design Part 5: Channel Operating Margin, a Powerful Compliance Tool | HyperLynx PCB Analysis
SERDES Clocking and Equalization for High-Speed Serial Links Transcript
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices
IBIS/AMI: Equalization in coming DDR standard | SPISim: EDA for Signal Integrity, Power Integrity and Circuit Simulation
Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices
Preemphasis and Equalization in GMSL SerDes Devices
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices
An Introduction to Preemphasis and Equalization in Maxim GMSL SerDes Devices
Optimize equalization for FFE, CTLE, DFE, and crosstalk - EDN
Feedforward Equalizer Location Study for High-Speed Serial Systems | 2019-04-29 | Signal Integrity Journal
SERDES Clocking and Equalization for High-Speed Serial Links Slides
Feedforward Equalizer Location Study for High-Speed Serial Systems | 2019-04-29 | Signal Integrity Journal
The technology of V-by-One® SerDes apply not only to TV application but to high-speed interfaces for communication/computer/industrial equipment as well|THine Electronics
PCIe 3.0 Equalization - EDN
SERDES Clocking and Equalization for High-Speed Serial Links Video
A tunable, power efficient active inductor-based 20 Gb/s CTLE in SerDes for 5G applications - ScienceDirect